how to get a T flip flop simulation waveform using Xilinx ISE design suite

Question

I tried to simulate a TFF using Xilinx ISE web pack and ModelSim using following block diagram and structural Code was written using VHDL. But I am unable to get the correct waveform. Due to the T-flip flop is sequential circuit, first I gave the output value as 1 or 0 for one output (Q) to start to the process.

T flip flop truth table and block diagram

simulation waveform

code for AND gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity AND_GATE is
Port ( X : in  STD_LOGIC;
       Y : in  STD_LOGIC;
          W : in STD_LOGIC;
       Z : out  STD_LOGIC);
end AND_GATE;

architecture Behavioral of AND_GATE is

begin
Z <= X AND Y AND W;

end Behavioral;

code for NOR gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NOR_GATE is
Port ( A : in  STD_LOGIC;
       B : in  STD_LOGIC;
       C : out  STD_LOGIC);
end NOR_GATE;

architecture Behavioral of NOR_GATE is

begin

c   <= A NOR B;

end Behavioral;

code for T-FF:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TFF_2 is
Port ( T : in  STD_LOGIC;
       CLK : in  STD_LOGIC;
       Q : inout  STD_LOGIC;
       s : inout  STD_LOGIC);
end TFF_2;

architecture STRUCTURAL of TFF_2 is

--declare components being used in T -FF
component TFF is
Port ( T : in  STD_LOGIC;
       CLK : in  STD_LOGIC;
       RST : in  STD_LOGIC;
       Q : out  STD_LOGIC);
end component;

component NOR_GATE is
Port ( A : in  STD_LOGIC;
       B : in  STD_LOGIC;
       C : out  STD_LOGIC);
end component;

component AND_GATE is
Port ( X : in  STD_LOGIC;
       Y : in  STD_LOGIC;
          W : in STD_LOGIC;
       Z : out  STD_LOGIC);
end component;

--declare signals

signal S1, S2 : STD_LOGIC;

begin

C1 : AND_GATE port map (Q, T, CLK, S1);
C2 : AND_GATE port map (S, T, CLK, S2);
C3  : NOR_GATE port map (S1, S, Q);
C4  : NOR_GATE port map (S2, Q, S);

end STRUCTURAL;

These files synthesized without any errors but in the simulation expected output was not given.

Answer 1

There are a few suggestions I have.

1. There are non initialised variables. Add := '0'; at the end of the declarations. Simulation might show "X" or unknown. The Synthesised design will work OK, being the hardware will go to one or zero, but simulators need to be directed.

2. Some of your output variables have feedback into inputs. The design is asynchronous, being that you are not using a clock of some description to time the iterations. Consider using a process and something like if rising_edge(clk)