I have a system verilog comparison as follows.
module m();
int count = 4;
logic [3:0] first = 14;
logic [3:0] second = 15;
initial begin
$display("Second %b\n", {count{1'b1}});
if(first == {count{1'b1}}) $display("FIRST Equals\n");
else $display("FIRST Not equal %b and %b\n", first, {count{1'b1}});
if(second == {count{1'b1}}) $display("SECOND Equals\n");
else $display("SECOND Not equal %b and %b\n", second, {count{1'b1}});
end
endmodule
This is the output
Second 1
FIRST Not equal 1110 and 1
SECOND Equals
What I did not understand is the print statements Second 1
and FIRST Not equal 1110 and 1
Why is it printing 1 instead of 1111?
One simulator tool I use generates compiler errors. According to IEEE Std 1800-2012 , section 11.4.12.1 Replication operator:
A replication operator (also called a multiple concatenation) is expressed by a concatenation preceded by a non-negative, non-x, and non-z constant expression, called a replication constant
With replication, I think you need to use a numeric constant, like 4, or a constant type, like parameter
.
parameter count = 4;
Another simulator I use generates warnings and produces the results you see.
The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.