Configuring Rocket Chip

Question

I want to build my own SOC based on the rocket chip without the use a ROCC(arm coprocessor). I checked this useful question: rocket chip on non zynq FPGA I looked for some detailed documentation but I only found few slides describing the configurations without an actual tutorial. Thus, I have three questions concerning the image below:

• I managed to generate the overall verilog for the tinyConfig, but is it possible to generate only the Rocket Chip, HostIO/AXI Convertor and MemIO/AXIHP Convertor? if yes how?
• Can a debug interface be added by the rocket Chip generator?
• Where can I change the RAM used in rocket chaip by a RAM of a specific FPGA vendor?

Answer 1

The verilog generated by rocket-chip can be used in FPGA. You just need to replace the behav_srams.v with the RAM generated in vivado.

In system/Config.scala, You can add class WithJtagDTMSystem to your config to generate debug interface.