SystemVerilog constraint: constrain the read address has been written before

Question

I want to write a constraint to make sure r_addr is only allowed when the same address has been used as w_addr before, but the following constraint doesn't work. Do you have any suggestion?

class try;
    rand int w_addr;
    rand int r_addr;
    int ua[$];
    int aa[int];
    constraint unique_addr_c{
        aa.size() == 0 || aa.exists(r_addr);
    }
endclass


module test;

    try a;

    initial begin
        a=new;
        repeat(20) begin
            if(a.randomize);
            $display("add=%0d", a.w_addr);
            $display("add=%0d", a.r_addr);
            a.ua.push_back(a.w_addr);
            a.aa[a.w_addr] = 1;
        end
    end

endmodule

Answer 1

You want to use the inside operator.

class try;
    rand bit [31:0] w_addr;
    rand int [31:0] r_addr;
    bit [31:0] ua[$];
    constraint unique_addr_c{
       ua.size() >0 -> r_addr inside {ua};
    }
    function void post_randomize();
       ua.push_back(w_addr);
       endfunction
endclass


module test;

    try a;

    initial begin
        a=new;
        repeat(50) begin
            if (!a.randomize) $error("randomization failed");
            $display("wadd=%0d", a.w_addr);
            $display("radd=%0d", a.r_addr);
        end
    end

endmodule

Notes: you should used unsigned types for addresses. Your check for randomize should produce an error.

Answer 2

Dave's answer is a great one.

Here is another one which uses a queue instead of an associated array.

class try;
rand int w_addr;
rand int r_addr;
int q[$];

function void post_randomize();
    int sz;
    int idx;
    q.push_back(w_addr);
    sz = q.size();
    idx = $urandom_range(0, sz-1);
    r_addr = q[idx];
endfunction
endclass

module test;

    try a;

    initial begin
       a=new;
       repeat(20) begin
           a.randomize();
          $display("sz=%0d w_addr=%x r_add=%x", a.q.size(), a.w_addr, a.r_addr);
       end
    end
endmodule

Answer 3

The following code works in mentor but not in synopsys

class bus;
rand bit [31:0] address;
rand bit rd_wr_en;
rand bit [1:0] interleaving;  
endclass

class my_bus;
rand bus b1[20];

function new();
 foreach(b1[n])
  b1[n] = new();
endfunction

constraint c {
  foreach (b1[n])
   if (n>0)
    if(b1[n-b1[n].interleaving].rd_wr_en ==1)
    { 
     b1[n].address == b1[n-b1[n].interleaving].address;
     b1[n].rd_wr_en == 0;
    }

   }

endclass
module tb;
my_bus b2;
 initial begin
 b2 = new();
 repeat (10) begin
   b2.randomize; 
   foreach(b2.b1[n])
   $display ( "%p", b2.b1[n]);       
   end
 end
endmodule