RISC-V Compressed Instructions: Can compiler be forced to align 32bit instructions on 32bit boundaries?

Question

We are implementing a custom RISC-V CPU. We start with Rocket core as the base and heavily modify.

Our first version was based on 2016 Rocket Chip, which did not have compressed instructions. We are now porting to 2017, which does. We recently discovered that the 2017 version allows 32bit instructions to be aligned on 16bit boundaries -- which means that a single instruction can be split across two cache lines!

For our implementation, this causes non-trivial issues.

Things are fine as long as 32bit instructions are not split across cache lines.

Can GCC be forced to align all 32 bit instructions on 32bit boundaries?

Answer 1

There is currently no support for this in the toolchain. Our GCC port would actually be incapable of doing this, as alignment is handled at link time (there's a blog on this: https://www.sifive.com/blog/2017/08/28/all-aboard-part-3-linker-relaxation-in-riscv-toolchain/ ). While you could add support for this to the toolchain, it'd render the C extension effectively useless so you're probably better off treating this as a core that doesn't support RVC.