How to synthesis Rocket-Chip on Vivado?

Question

I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I dont get the same results. I used the 2 files generated after running 'make verilog' in vsim directory. For synthesis I defined the variable 'SYNTHESIS'. What are the things I might me missing go get appropriate results?

Answer 1

您应该首先生成 Verilog 输出，将其合并到您的系统或 SoC 中，然后像往常一样将其传递给 Vivado