case? VHDL2008 matching case statement

Question

VHDL 2008 introduced a nice feature called "matching case statement".

Should I use "case?" keyword or "case ?" with a space in between also allowed?

It is not clear for me. Lattice LSE allows both of them. Synplify accepts only the first one.

The definition (section 10.9) from the standard is:

case_statement ::=
    [ case_label : ]
    case [ ? ] expression is
        case_statement_alternative
        { case_statement_alternative }
    end case [ ? ] [ case_label ] ;

Answer 1

case? is the keyword. No Space.

Answer 2

In the VHDL-2008 Language Reference Manual (IEEE Std 1076-2008) chapter 15.3 it is written that

One or more separators are allowed between any two adjacent lexical elements, before the first of each design unit, or after the last lexical element of a design file. At least one separator is required between an identifier or an abstract literal and an adjacent identifier or abstract literal.

A space character is defined in the same chapter as one of the separators. Both the "case" and "[ ? ]" are lexical elements.

So both "case?" and "case ?" are valid. The one you should use is "case?" since that's the one that works with all your tools.