Variable use in VHDL

Question

I was reading some codes in VHDL and saw this example:

  signal     count : integer range 0 to width;
begin
  process(clk, rst)
    variable temp  : integer range 0 to width;
begin
          temp := count + 1;
          count <= temp;
end process;

what's the purpose of count signal here? Why can't we just use the variable?

Answer 1

Variables are local to the process, and signals are used to communicate between processes.

So you would rather do without the variable, and in the process just have:

count <= count + 1;