How to initialize a variable with n number of bits in VHDL?

Question

so basically I'm trying to do a multiplier in VHDL with 2 inputs of N bits with an output of 2*N bits. I'm just a beginner in this language so I've tried to make a simple code without using some advanced tools/terms. So here's what I've got:

My code in VHDL

Their is an error right between the initialization of the variables and the loop. I think that everything after the loop is correctly written so the problem can only be the variables. I want to have variables that could, like the entries, have a variable number of bits depending on N (initialize in Generic). I also want to initialize some of their bits to 0.

Bvariable would only be half of the bits (The MSB) and the other half would take the bits of Y.

Pvariable would have all of his bits with the value 0.

Some addition info for variables for those who want more clarification:

1.The Bvariable is B with more bits and shifted to the left in the loop.

2.The Pvariable is P but we're changing constantly his value before attribute it to P.

Here's my problem. Hope that you could help me find answers. Also, feel free to propose me another way to build a multiplier if it is relatively simple (like with signals instead of variables).

Thank you for your time.

My code in VHDL

Answer 1

You can simply use the resize function for an existing unsigned:

variable Bvariable : unsigned(2*N-1 downto 0) := resize(Y, Bvariable'length);

or the to_unsigned function for an integer literal

variable Pvariable : unsigned(2*N-1 downto 0) := to_unsigned(0, Pvariable'length);