VHDL: Using type 'time' in generic map

Question

I have a generated unit, which uses generics of type 'time'. When I try to map these generics, my simulator croaks during elaboration with the message: 'illegal generic map aspect'. Is it illegal to have a generic map like this?

inst: mod_name
generic map (
   delay_val => 12 ns
)
...

or is just my simulator not able to cope with this?

Note: As the unit is generated code, I can't just change the type to integer and do some casting inside. Such changes would be overwritten each time, the code is generated anew, which happens from time to time.

Answer 1

A small test case for this "problem" looks like this. But this compiles without any warning or error message. So this is perfectly valid VHDL (as expected) and my issue is a tool problem, that I have to deal with my tool vendor.

Sub-Module:

library ieee;
use ieee.std_logic_1164.all;

entity clk_gen is
  generic (
    clk_period : time := 10 ns
  );
  port (
    clk : out std_logic
  );
end clk_gen;

architecture beh of clk_gen is
  signal clk_int : std_logic := '0';
begin  -- beh

  clk <= clk_int;
  
  ckg: process
  begin
    clk_int <= not clk_int;
    wait for clk_period/2;
  end process ckg;
  
end beh;

Test bench:

library ieee;
use ieee.std_logic_1164.all;

entity tb_clk_gen is
  -- empty
end tb_clk_gen;

architecture beh of tb_clk_gen is
  signal clk : std_logic;
begin  -- beh

  ckg: entity work.clk_gen(beh)
    generic map (
      clk_period => 12 ns
    )
    port map (
      clk => clk
    );

end beh;