Why won't a signal be updated instantly in process statement? VHDL

Question

In VHDL, you need to use a variable in a process statement for it to be updated instantaneously. The use of a signal can be done, but it won't be updated immediately. Repeating my question from above: Why won't a signal be updated instantly in process statement?

Answer 1

You're thinking like software. A signal is a physical line that (usually) has a logic level of 0 or 1. An assignment to it within a clocked process is queuing up the value that will come out of a flip-flop one the next clock edge (rising or falling, depending on how the process is written).

A variable doesn't exist in the final hardware and is only a placeholder for your convenience.