如何设置 emitVerilog 的生成目录？

Question

I just started with chisel-template.

I added below statement in DecoupledGCD.scala per a stackoverflow post .

object DecoupledGcdDriver extends App {
    (new ChiselStage)emitVerilog(new DecoupledGcd(16))
}

When I ran

sbt run

The verilog file was generated in current directory per se.

However either I run

sbt "runMain gcd.DecoupledGcdDriver --help"

or

sbt "runMain gcd.DecoupledGcdDriver --target-dir <my dir>"

doesn't change anything.

My build.sbt is from latest template:

ThisBuild / scalaVersion     := "2.12.13"
ThisBuild / version          := "0.1.0"
ThisBuild / organization     := "com.github.riggy2013"

lazy val root = (project in file("."))
  .settings(
    name := "chisel-gcd",
    libraryDependencies ++= Seq(
      "edu.berkeley.cs" %% "chisel3" % "3.4.3",
      "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test"

I don't have enough "reputation" so start a new thread here.

Answer 1

Set the arguments as a call to the ChiselStage . Below is an example. This will put the Verilog and FIRRTL in the output dir. The output dir will be created if it doesn't exists.

object MyAsyncResetModuleGen extends App {  
  val myverilog = (new ChiselStage).emitVerilog(
    new MyAsyncResetModule,
     
    //args
    Array("--target-dir", "output/")
  )
}

Answer 2

Extending App is just syntactic sugar for writing a main function with the argument args: Array[String] . If you want the arguments to propagate to ChiseStage , you need to propagate them:

object DecoupledGcdDriver extends App {
    (new ChiselStage)emitVerilog(new DecoupledGcd(16), args)
}

You can see that ChiselStage.emitVerilog accepts args in the Chisel API Docs .