Difficulties with assigning a generic in VHDL

Question

I am relatively new to VHDL and am facing problems with generics. I want to assign a signal value to a generic. Can that be done?

architecture rtl of entity_name is  

  signal ibaudratetop: integer;  

  component my_baud1 is  
    generic(  
      baudrate       : integer := 115200;  
      clock_freq_mhz : real    := 1.843200);  
    port(  
      clk  : in std_logic;  
      rst  : in std_logic;  
      baud : out std_logic);  
  end component;  

begin  

  BAUDRATE: my_baud1  
    generic map(  
      baudrate       => ibaudratetop,  
      clock_freq_mhz => 1.843200)  
    port map(
      clk  => clk,  
      rst  => rst,  
      baud => ibaudrx);  

end rtl;

This is only a part of my UART code. Is that type of generic mapping possible where a signal which is of type integer is assigned to a generic? I am unable to simulate the code.

Answer 1

No, generics are evaluated during elaboration (kind of "compile time") and signal is expected to change during simulation (so more like "run time").

So if an input should change after the compilation and elaboration then better use a port.