How to overloading an operator in SystemVerilog
Question
Does anyone have a working example for overloading an operator in SystemVerilog? I read the spec and tried "bind" with Questasim 10.3. But there's no luck.
1 answers
solution1
3 ACCPTED 2015-02-14 06:58:27
我认为没有任何工具支持此构造。
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