inside operator to include every element of systemverilog enum

Question

Is there a way to use inside operator for every element of enum ? for eg I've the following enum :

typedef enum {ADD, SUB, MUL, DIV, MOD} Instr_t;

While writing constraints or checking if received opcode is any one of the valid Instructions, is there an easier way I've tried the following:

if (opcode inside {Instr_t})

This fails and I need to use expanded enum :

if (opcode inside {ADD, SUB, MUL, DIV, MOD})

This is easy when enum is small but gets annoying with bigger enum , other way I could think is using define .

Answer 1

There's no need for this constraint. The constraint solver is not allowed to assign a value to a random enum variable that is outside the set of declared enum labels.

The IEEE just approved a clarification to the LRM that will be release in the next update to the standard.

https://accellera.mantishub.io/view.php?id=4939

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Update

If you want to create instruction subsets, you can put groups of enum labels into an array, and use the array with the inside operator

typedef enum {ADD, SUB, MUL, DIV, MOD,OR, AND, XOR} opcode_t;
const opcode_t arithmetic_ops[] = {ADD, SUB, MUL, DIV, MOD};
const opcode_t logical_ops[] = {OR, AND, XOR};


if (opcode inside {arithmetic_ops})

Answer 2

You need to first declare a variable of that enum and use it with inside.

For example:

opcode_t op; 
if(opcode inside {op}) 
//continue

Answer 3

If you wish to check a value against the entire enum space, you can do:

opcode_t op = opcode_t'(42);
if (op.name()=="") begin
  $display("Invalid opcode: %s (%d)", op.name(), op);
end