How can I use genvar variable to access input signals?

Question

I have a module with 30-vector inputs.. I need help in the for loop assignment.

module test (
  input [3:0] i0,
  input [3:0] i1,
  input [3:0] i2,
  ...
  input [3:0] i29

);

wire [3:0] int_i [0:29];

genvar j;
generate
  for (j=0; j<30; j=j+1) begin
    assign int_i[j] = i(j) //need help here 
  end
endgenerate


endmodule

Is there a easy way to do this in Verilog. I know I can do this in System verilog by creating a 2-d vector of inputs. But is there a way to do this in Verilog?

Answer 1

The only way to do this in Verilog is to flatten out the 2-D array into a single vector.

module test (
  input [30*4-1:0] i;
);
wire [3:0] int_i [0:29];
genvar j;
for (j=0; j<30; j=j+1) begin
    assign int_i[j] = i[4*j+:4];
end

Answer 2

This is a systemverilog feature, in verilog, this should be packing the input array into a vector (I included a parameter in order to automatize things):

module test
# (
   parameter WIDTH = 4,
   parameter DEPTH = 30
  ) (input [(WIDTH*DEPTH)-1:0] i);

wire [WIDTH-1:0] int_i [DEPTH-1:0];
genvar j;

generate
 for(j=0; j<DEPTH; j=j+1) begin: assign_i_gen //..(don't forget to name the for loop)
   assign int_i[j] = i[(WIDTH*j)+:WIDTH];
 end
endgenerate