[英]How to convert this SystemVerilog sim to Verilog
我正在编写有关Verilog中SPI Master实现的教程。 我已经非常了解该模块的工作原理以及不同模块的功能。
但是现在我开始使用SystemVerilog编写的仿真。 而且我正在使用不支持SystemVerilog的Xilinx ISE设计套件(我有Mimas V2-Spartan 6 FPGA开发板)。
我的问题是,如何在Verilog中编写SystemVerilog仿真?
我试图用reg替换逻辑类型,但是我不知道.sv
和.v
之间的其他区别是什么。
///////////////////////////////////////////////////////////////////////////////
// Description: Simple test bench for SPI Master module
///////////////////////////////////////////////////////////////////////////////
module SPI_Master_TB ();
parameter SPI_MODE = 3; // CPOL = 1, CPHA = 1
parameter CLKS_PER_HALF_BIT = 4; // 6.25 MHz
parameter MAIN_CLK_DELAY = 2; // 25 MHz
logic r_Rst_L = 1'b0;
logic w_SPI_Clk;
logic r_Clk = 1'b0;
logic w_SPI_MOSI;
// Master Specific
logic [7:0] r_Master_TX_Byte = 0;
logic r_Master_TX_DV = 1'b0;
logic w_Master_TX_Ready;
logic r_Master_RX_DV;
logic [7:0] r_Master_RX_Byte;
// Clock Generators:
always #(MAIN_CLK_DELAY) r_Clk = ~r_Clk;
// Instantiate UUT
SPI_Master
#(.SPI_MODE(SPI_MODE),
.CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)) SPI_Master_UUT
(
// Control/Data Signals,
.i_Rst_L(r_Rst_L), // FPGA Reset
.i_Clk(r_Clk), // FPGA Clock
// TX (MOSI) Signals
.i_TX_Byte(r_Master_TX_Byte), // Byte to transmit on MOSI
.i_TX_DV(r_Master_TX_DV), // Data Valid Pulse with i_TX_Byte
.o_TX_Ready(w_Master_TX_Ready), // Transmit Ready for Byte
// RX (MISO) Signals
.o_RX_DV(r_Master_RX_DV), // Data Valid pulse (1 clock cycle)
.o_RX_Byte(r_Master_RX_Byte), // Byte received on MISO
// SPI Interface
.o_SPI_Clk(w_SPI_Clk),
.i_SPI_MISO(w_SPI_MOSI),
.o_SPI_MOSI(w_SPI_MOSI)
);
// Sends a single byte from master.
task SendSingleByte(input [7:0] data);
@(posedge r_Clk);
r_Master_TX_Byte <= data;
r_Master_TX_DV <= 1'b1;
@(posedge r_Clk);
r_Master_TX_DV <= 1'b0;
@(posedge w_Master_TX_Ready);
endtask // SendSingleByte
initial
begin
// Required for EDA Playground
$dumpfile("dump.vcd");
$dumpvars;
repeat(10) @(posedge r_Clk);
r_Rst_L = 1'b0;
repeat(10) @(posedge r_Clk);
r_Rst_L = 1'b1;
// Test single byte
SendSingleByte(8'hC1);
$display("Sent out 0xC1, Received 0x%X", r_Master_RX_Byte);
// Test double byte
SendSingleByte(8'hBE);
$display("Sent out 0xBE, Received 0x%X", r_Master_RX_Byte);
SendSingleByte(8'hEF);
$display("Sent out 0xEF, Received 0x%X", r_Master_RX_Byte);
repeat(10) @(posedge r_Clk);
$finish();
end // initial begin
endmodule // SPI_Slave
这是输出:
ERROR:HDLCompiler:1366 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 53: Multiple statement function/task without begin/end not supported in this mode of Verilog
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 12: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 13: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 14: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 15: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 18: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 19: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 20: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 21: logic is an unknown type
ERROR:HDLCompiler:1059 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 22: logic is an unknown type
ERROR:HDLCompiler:598 - "/home/ise/SPIMaster/SPI_Master_TB.v" Line 6: Module <SPI_Master_TB> ignored due to previous errors.
由程序编码分配的logic
(例如: always
block, task
和function
)应转换为reg
以实现其Verilog等效功能。
连续分配(例如: assign
语句,或模块实例上的输出)分配的logic
应转换为wire
,以实现其Verilog等效功能。
在您的特定情况下,看起来所有以“ r_”开头的logic
都应为reg
而“ w_”则应为wire
Verilog要求任务/功能的主体代码必须以一个begin
end
括起来(SystemVerilog会自动推断出这一点)。 您对此的错误消息应该是不言自明的。
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