[英]Is it legal to have an independent if-clause for the D flip-flop reset in VHDL?
I have the following code describing some registers:我有以下代码描述了一些寄存器:
DCR_WR_REGS_P: process (CLK)
begin
if rising_edge(CLK) then
if DCR_WRITE = '1' then
if C_BASEADDR(0 to 6) = DCR_ABUS(0 to 6) then
case to_integer(unsigned(DCR_ABUS(7 to 9))) is
when REG_DMA_RD_ADDR_OFFS =>
dma_rd_addr_reg <= DCR_WR_DBUS (0 to DMA_RD_ADDR_SZ-1);
when REG_DMA_RD_LENG_OFFS =>
dma_rd_leng_reg <= DCR_WR_DBUS (0 to DMA_RD_LENG_SZ-1);
rd_dma_req <= '1';
-- more registers here...
when
when
----------------------
when others =>
end case;
end if;
else
if clear_rd_dma_req='1' then
rd_dma_req <='0';
end if;
end if;
end if;
end process DCR_WR_REGS_P;
This code works except for the fact that the clear_rd_dma_req is ignored when DCR_WRITE is active.除了当 DCR_WRITE 处于活动状态时会忽略 clear_rd_dma_req 之外,此代码有效。 So, can I somehow make the "if clear_rd_dma_req='1'" clause an independent one?那么,我可以以某种方式使“if clear_rd_dma_req='1'”子句成为一个独立的子句吗? I realize that I can create a separate process just for the rd_dma_req bit, but I am trying to avoid that as I have a few bits like that.我意识到我可以为 rd_dma_req 位创建一个单独的进程,但我试图避免这种情况,因为我有一些这样的位。
Here's a version with a separate process:这是一个具有单独过程的版本:
DCR_WR_REGS_P: process (CLK)
begin
if rising_edge(CLK) then
if DCR_WRITE = '1' then
if C_BASEADDR(0 to 6) = DCR_ABUS(0 to 6) then
case to_integer(unsigned(DCR_ABUS(7 to 9))) is
when REG_DMA_RD_ADDR_OFFS =>
dma_rd_addr_reg <= DCR_WR_DBUS (0 to DMA_RD_ADDR_SZ-1);
when REG_DMA_RD_LENG_OFFS =>
dma_rd_leng_reg <= DCR_WR_DBUS (0 to DMA_RD_LENG_SZ-1);
-- more registers here...
when
when
----------------------
when others =>
end case;
end if;
end if;
end if;
end process DCR_WR_REGS_P;
RD_DMA_REQ_P: process (CLK)
begin
if rising_edge(CLK) then
if clear_rd_dma_req='1' then
rd_dma_req <='0';
elsif DCR_WRITE = '1' then
if C_BASEADDR(0 to 6) = DCR_ABUS(0 to 6) then
if to_integer(unsigned(DCR_ABUS(7 to 9))) = REG_DMA_RD_LENG_OFFS then
rd_dma_req <= '1';
end if;
end if;
end if;
end if;
end process RD_DMA_REQ_P;
And here's a version with an independent if-clause, which is probably illegal:这是一个带有独立 if 子句的版本,这可能是非法的:
DCR_WR_REGS_P: process (CLK)
begin
if rising_edge(CLK) then
if DCR_WRITE = '1' then
if C_BASEADDR(0 to 6) = DCR_ABUS(0 to 6) then
case to_integer(unsigned(DCR_ABUS(7 to 9))) is
when REG_DMA_RD_ADDR_OFFS =>
dma_rd_addr_reg <= DCR_WR_DBUS (0 to DMA_RD_ADDR_SZ-1);
when REG_DMA_RD_LENG_OFFS =>
dma_rd_leng_reg <= DCR_WR_DBUS (0 to DMA_RD_LENG_SZ-1);
rd_dma_req <= '1';
-- more registers here...
when
when
----------------------
when others =>
end case;
end if;
end if;
if clear_rd_dma_req='1' then
rd_dma_req <='0';
end if;
end if;
end process DCR_WR_REGS_P;
Thanks谢谢
Yes you can make it an independent one (still inside the if rising_edge(clk)
statement).是的,您可以将其if rising_edge(clk)
独立的(仍在if rising_edge(clk)
语句中)。 What makes you think this version (last in the modified question) should be illegal?是什么让您认为此版本(修改后的问题中的最后一个)应该是非法的?
Anything it does will override assignments made to the same signals by the if DCR_Write
statement, thanks to the "last assignment wins" rule.由于“最后一次分配获胜”规则,它所做的任何事情都将覆盖由if DCR_Write
语句对相同信号if DCR_Write
分配。
HOWEVER why not simply reverse the prioritisation and tidy it up, like this?然而,为什么不简单地颠倒优先顺序并整理它,像这样呢?
if clear_rd_dma_req='1' then
...
elsif DCR_Write = '1' then
...
end if;
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