Multidimensional memory with generic data width VHDL

Question

I would like to know how to declare a 2-dimensional memory with a generic data width

package mem_pkg is
  subtype data is std_logic_vector(7 downto 0);
  type data_vector is array( natural range <> ) of data;
end;
entity mem is
port (
  clk : in std_logic;
  we : in std_logic -- write enable
  a: in unsigned(4 downto 0); -- address
  di : in data; -- data_in
  do : out data -- data_out
 );
 end mem;

---

Instead of 7, I want the data width to be generic.

Answer 1

That's not two dimensional - that's a vector of vectors, which is (subtly) different.

A 2D array is

type data_vector is array (natural range <>, natural range <>) of integer;

But, back to your problem:

Until "recently" (VHDL 2008) you couldn't have an unconstrained array of an unconstrained array. But now you can do:

type mem is array(natural range <>) of std_logic_vector;
signal store : mem(0 to 15)(7 downto 0);

" VHDL 2008 - just the new stuff " has much more detail:

http://books.google.co.uk/books?id=ETxLguPMEY0C&lpg=PA241&ots=q7u_Mn0SFR&dq=vhdl%202008%20just%20the%20new%20stuff%20p%20120&pg=PA120#v=snippet&q=alias%20of%20a%20register%20file%20signal&f=false