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VHDL how to generate multiple flip flop entities to use BIT_VECTOR as D-input

I am trying to use the generate function to make multiple flip flops to be used a register. I have a signal bit vector which i would like each bit to be the D input into its equivalent flip flop but after compiling i get the warning that the output Q has no driver.

Here i define the behaviour of the flip flop

entity flipflop is
    port( 
        D,CLK,RST: in BIT;
        Q: out BIT
    );
    end entity;
architecture behavioral of flipflop is
begin
    P1: process(RST,CLK)
    begin
        if(RST='1')then
            Q <= '0';
        elsif(CLK='1' and CLK'EVENT) then
            Q <= D;
        end if;
    end process;
end behavioral;

I then generate 32 flip flops and try to set each bit of the bit_vector signal sum to each of the D inputs of the flip flops.

    SIGNAL Q,D: BIT_VECTOR (31 DOWNTO 0);
    SIGNAL SUM: BIT_VECTOR (31 DOWNTO 0);
BEGIN
    register_maker : for i in 0 to 31 generate 
    BEGIN
        flipflop_inst : ENTITY work.flipflop port map
            (Q => Q(i),
            CLK => CLK,
            RST => RST,
            D => D(i)
        );
    end generate register_maker;

    process (D,SUM)
    begin
        for i in 0 to 31 loop   
            D(i) <= SUM(i);
        end loop;
    end process;

I'm not sure where i am going wrong but the outputs of the flip flops are not changing.

Thanks

The process (D,SUM) should not be dependent on DIe you only want D to change when sum changes. As they have equal length, this can simply be done with:

D <= SUM;

Then you say the outputs of the flipflops are not changing. Could it be because RST is stuck at '1' in you testbench? (We all made that mistake ;) )

And may I ask why are you not using std_logic and std_logic_vector ?

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