Specifying a target in a makefile without having it show up in $^

Question

I have a program that links against aa library that is also in the process of development. I want to re-link my program when the library changes (and therefore have the .a file in my list of prerequisites, but I also want to be able to use the $^ automatic variable (or something like it) to list all of the other targets in the invocation of the linker. I may also list the makefile itself as a dependency for some targets, to ensure they get recompiled if I change the makefile.

Is there some way I can flag a particular file as a dependency without having it show up in automatic variables like $^ ?

Answer 1

I don't know of any way to modify $^ itself, but GNUMake has some good functions for manipulating text , such as filter-out :

foo: bar baz quartz.a Makefile
    @echo I want $(filter-out %.a Makefile, $^), not $(filter %.a Makefile, $^)